Key input indicating system

ABSTRACT

A key information indication system is incorporated into an electronic digital apparatus equipped with a key board for entering input information into the interior of the apparatus and an indication device for indicating the entered information. The system in particularly adapted to avoid indication of any futile or insignificant information such as undesired &#39;&#39;&#39;&#39;zeros&#39;&#39;&#39;&#39; in digit positions exceeding the most significant digit of the effective decimal numbers introduced by the keys. A suppression register N having a capacity of a predetermined number of bits corresponding to the digit capacity of a main register X is provided for counting the number of key depressions and providing suppresion signals to inhibit indication of the insignificant information. The input information from the key board is directly coupled with the suppression register N to provide a suppression signal during information entry modes to accomplish the desired indication suppression without necessitating detection of any digit other than &#39;&#39;&#39;&#39;zero&#39;&#39;&#39;&#39; stored in the suppression register.

United States Patent 1 Teramura et a]. k

[ KEY INPUT INDICATING SYSTEM [75] Inventors: Satoshi Teramura, l, Tomigaoka, Nara-shi; Kazuyuki Kurata, i500 Tsutsui-cho, Yamatokoriyama, both of Japan [73] Assignee: Sharp Kabushiki Kaisha, Osaka,

Japan [22] Filed: Mar. 5, 1973 [2]] Appl. No: 337,855

[30] Foreign Application Priority Data Mar. 6, 1972 Japan 47-22889 [52] 1.5. CI. 340/1725; 235/92 PL [51] Int. Cl. G06f 3/00 [58] Field of Search 340/1725; 235/92 PL, 92 EA [56] References Cited UNITED STATES PATENTS 3,636,319 l/l972 Nixon 235/92 EA 3,732,545 5/1973 Hatano et a]. 340/1725 Primary Examiner-Raulfe B. Zache Attorney, Agent, or Firm--Stewart and Kolasch, Ltd.

DECIIAL Nil" REEISTER July 1, 1975 5 7 ABSTRACT A key information indication system is incorporated into an electronic digital apparatus equipped with a key board for entering input information into the interior of the apparatus and an indication device for indicating the entered information. The system in particularly adapted to avoid indication of any futile or insignificant information such as undesired zeros" in digit positions exceeding the most significant digit of the effective decimal numbers introduced by the keys. A suppression register N having a capacity of a predetermined number of bits corresponding to the digit capacity of a main register X is provided for counting the number of key depressions and providing suppresion signals to inhibit indication of the insignificant information. The input information from the key board is directly coupled with the suppression register N to provide a suppression signal during information entry modes to accomplish the desired indication suppression without necessitating detection of any digit other than zero stored in the suppression register.

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SECOND swam-[1T] KEY INPUT INDICATING SYSTEM BACKGOUND OF THE INVENTION This invention relates to an input information indication system, and more particularly to an improved input information entry and indication system which provides inhibitation signals avoiding indication of any insignificant infonnation during the entry process of key input information.

This invention is particularly applicable to electronic desk-top calculators, electronic cash registers, electronic price computing scales, etc., in which the entering inputs and the results of calculation are indicated as a series of numbers or digits by the use of indicator tubes.

According to the prior art implementations, to accomplish the avoidance of the indication of ineffective zeros in both the cause of indications of contents of key input information and resultant information, the contents stored in a main register are examined by a detection circuit responsive to a digit other than zero, which thus decides significances of the information applied therein. The output from the detection circuit is then applied to an additional register, the outputs of which directly control inhibition and allowance of the indication of information. In other words, in both cases the contents to be displayed are required to stand in the main register in the same manner and especially in the case of indicating of key inputs, the contents of key inputs are first applied to the main register during the process of key input entry and thereafter the contents stored in the main register are read out to provide indication of key input entry. At this moment the zero suppression is required. Thus, for purpose of the avoidance of ineffective information in the key input information the entry and withdrawal of the key information into and from the main register is required and repeated at every entry process. Furthermore, a detection circuit is needed for detecting any digit other than zero. The prior art attempts, therefore, were time consuming and complicated. A more detailed description of prior art attempts is found in U.S. Pats. Nos. 3,449,726 and 3,662,346.

OBJECTS AND SUMMARY OF THE INVENTION Accordingly, the primary object of this invention is to provide an improved key input indication system which avoids one or more of the disadvantages and limitations of the above conventional devices.

Another object of this invention is to provide an improved key input indication system which is capable of avoiding the indication of insignificant information during the process of key input entry to a main register within an electronic digital apparatus.

Still another object of this invention is to provide a key input indicating system which is peculiarly suitable for avoidance of the indication of ineffective zeros in a series of display tubes during the key input entry process.

A further object of this invention is to provide a key input indication system which can accomplish ineffective zero-suppressed indication without necessitating entry and withdrawal of the key information into and from a main register.

Another object of this invention is to provide a key input indicating system which achieves the simultaneous provision of the avoidance of ineffective indication and the entry of key input information into a main register in a binary code fashion.

It is still a further object of this invention to provide a key input information entry and display system which can accomplish the ineffective zero-suppressed indication without necessitating detection modes of any digits other than zero.

In summary, this invention provides a key input information indicating system comprising a plurality of keys for entering individual key inputs upon the manual depression thereof, a series of indicating elements for indicating the entered key input, a counter suppression register responsive to the key inputs for counting the number of the manual depressions of the keys, the outputs of the counter suppression register being indicative of the number of key inputs to be actually indicated, and a connection coupling the counter outputs with the indicating elements thereby inhibiting the indication of insignificant information in the series of the indicating elements.

These and other objects and novel features of this invention are set forth in the appended claims and this invention as to its organization and its mode of operation will best be understood from a consideration of the following detailed description of the preferred embodiments when used in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a schematic block diagram illustrating an exemplary digital apparatus wherein this invention is embodied.

FIG. 2 is a schematic block diagram illustrating an embodiment of a key input indicating system in accordance with this invention.

FIG. 3 is a circuit diagram illustrating an indicating device within the system of FIG. 2.

FIG. 4 is a time chart illustrating the relation of various timing signals used in the FIG. 2 embodiment.

FIGS. SA-SD are diagrams which further explain the operation mode of the FIG. 2 embodiment.

FIG. 6 is a schematic block diagram illustrating another embodiment of the key input indicating system.

FIG. 7 is a diagram which further explains the operation of the FIG. 6 embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The following description is directed to an examplary electronic desk-top calculator wherein this invention is embodied, although this invention is applicable to other electronic appartus, such as electronic cash registers, electronic weighing machines, etc.

Referring now to FIG. I, there are provided two kinds of inputs for controlling the whole system, namely, information relating to numerical values and instructions as to the operation of processing that information by means of an input device. The input device includes a lO-key type keyboard KB provided with numeral keys 0 through 9, a decimal point key and operational function keys X, etc., and can introduce the key signals relating to numerical values and operation processing through desired ones of the keys manually depressed by an operator. The numerical processing section of the input device is directly coupled to a main register X and a decimal point register .1: and numerical information and decimal point infonnation is respectively written in the registers X, X. The operation indication section of the input device is directly coupled to a control unit C containing a program matrix, conditional flip-flops, etc.

It is assumed that the numerical values processed in this system are of binary coded decimal notation (four bits in each digit) and the register X has a capacity of 16 digits (4 X 16 bits) wheras the decimal point register x has a capacity of 16 bits.

The control unit C generates micro orders necessary for execution of various arithmetic operations and the micro orders are introduced into inputs of logic gates provided between various sections of the calculator to control flows of numerical information therebetween. A clock pulse generator CP is provided for generating a train of clock pulses (not shown) used for a standard of synchronous control of various devices and a timing signal generator TC variously modifies the clock pulses to produce digit time signals T, through T word time signals CPC and so forth as shown in FIG. 4. The digit timing signals T T, represent a time scale indicative of weights of digits in the case of viewing the information serially circulating through the register from the outputs thereof. The clock pulses d D occur every one digit time period.

An indication device DP contains a series of indication or display tubes DP, through DP (such as, fluorescent type tubes) of a 16 digit capacity which is the same capacity as the main register X, thereby providing digital indication of the contents stored in the register X. As viewed from FIG. 3, the indication device is of a dynamic type wherein the information serially delivered is commonly supplied to all of the indication tubes DP, through DP via a decoder DC while the digit time signals T through T are supplied to the respective individual tubes DP to sequentially energize them.

FIG. 2 illustrates an embodiment of the key input storage and indication controlling arrangement which is an important feature. A supperssion register N is of a capacity of 16 bits, the contents of which are stored by circulation synchronous with shift operations in the main register X. The suppression register N stores in formation for the purpose of the avoidance of insignificant indication and thus stores 1 in certain bit positions corresponding to the digit positions in the indication tube series to be indicated. As viewed from FIG. 3, application of the timing signals into the corresponding indicating tubes is under the control of outputs of the suppression register N. That is, the indication tubes DP p are only energized when both the timing signals and the outputs of the register N applied therein are l.

Depression of the numeral key or decimal point key provides a key depression signal K, which in turn is introduced into an entry control circuit PK for determining timings of entry mode into the main register X. The control circuit PK thus provides an entry controlling signal P having one word time period synchronous with the clock pulses CPC and the key depression signal K. The entry controlling signal P is applied to input gates to the registers X, N to control the entry of information into the registers X, N.

In general, the operation mode of key signal entry may be divided into two kinds: (i) The first mode is called first entry mode" which is required to introduce new numerical information into the most significant digit place after the depression of any operational function keys X, etc., or completion of arithmetic operations. This mode will eliminate all of the previous contents in the main register X and also the previous contents in the suppression register N. At this time new numerical value is entered into the most or least significant digit place X16 or X1 of the main register X and l is entered into the corresponding bit position X16 or XI of the suppresion register N. (ii) The second mode is called second entry mode which follows the above first entry mode and is required to enter the succeeding numerical values into the corresponding digit places other than the most or least significant digit place of the main register X. This mode also causes the succeeding numerical values to be introduced to the left or right of the first entered numerical information and the corresponding bit positions of the suppresion register N to store I.

The key input entry and indication controlling operation according to this invention requires a discrimination between the first and second entry modes. FIG. 2 illustrate an example which is constructed and arranged to enter consecutively the numerical key inputs in descending order of significance, i.e., from the most significant digit to the least significant digit. Therefore, in this instance, the first entry mode is accomplished against the most significant digit position X16 while the second entry modes are accomplished against the succeeding digit positions X15 X7, in descending order. The suppression register N provides differences in operation modes between the first and second entry processes.

As seen from FIGS. 5(A) through 5(D), the entry modes as to the numerical information are, in fact, divided into three cases, namely, a numerical key 0, other numerical keys I through 9, and a decimal point key For example, depression of the numerical key 1 causes an encoder EC to produce serial binary coded decimal numbers indicative of decimal number 1 and initiates the key depression signal generator PK. Simultaneously, the key signals are applied to a set input terminal of a decision flip-flop B, and AND gates AGl, AG2 via OR gates 0G2, 063 while the inversion thereof are applied to AND gates A03, AG4. The decision flip-flop B detects distinction between the first entry mode and the second entry modes, and for example is reset in response to depression of the function key FK, the reset conditions thereof being representative of the first entry mode. The operational conditions of the decision flip-flop B are synchronous with the signals P'CPC.

In this case the numerical information (binary codeddecimal number is introduced into the most significant digit place X16 of the main register X because the digit time signal T16 opens an AND gate G1 via an inhibition gate 161. The AND gate AG3 is closed by outputs from an OR gate 0G3 during one word time period from occurrence of the entry control signal P to application of the digit time signal T16 to eliminate all of the previous contents of the register X preceding the entry mode.

In the meanwhile, the contents of the suppression register N all disappear because AND gate AG4 is closed. The most significant bit position N16 of the suppression register N receives and stores I at the timing when the digit time signal T16 opens the AND gate 02 through an AND gate AGS. If no key depression occurs therafter. the contents of both the registers X, N

are circulated and stored through the AND gates AG3, AG4. During the circulation process the suppression register N provides I only to the indication tube DP16 in the most significant digit position to energize it and thus the indication tubes DPl through DP in the remaining digit positions are all de-energized to inhibit the useless indication of ineffective zeros.

In the case of the first entry relating to the numerical key 0, the coded decimal number indicative of 0 is introduced into the most significant digit position X16 of the register X in the same manner as the other numerical keys 1 through 9. However, the suppression register N does not recive any information since the logical conditions are not established for the AND gate AGS. It will be understood that the supperssion register N does not respond to a key depression corresponding to the first entry relating to the numerical key 0.

When the decimal point key is manually depressed under the reset conditions of the decision flip-flop B, the contents of the register X disappear but then the suppression register N receives 1 in the most significant bit position N16 thereof. This is due to the fact that the key signals from the decimal point key opens the AND gate AGS through the OR gate 064 as well as the opening of the gates AG2,AG4 through an AND gate AG6 and OR gate 063. The most significant bit position of the decimal point register 2: stores I, which activates a decimal point segment of the indication tube DP16 at the timing T16. The decision flip-flopf B is reset through a loop containing the decimal point key AND gate AG6 and OR gate 0G3 and thereafter interprets the next key entry as the second entry mode.

The second key entry mode is treated as follows.

When one of the numerical keys, for example, 2 is manually depressed after completion of the first key entry mode, the following operations are caused to occur: entry and storage of 1 into the bit positions N16, N15 of the suppression register N, and entry and storage of l, 2 into the digit positions X16, X15 of the main register X. As illustrated in FIG. 2, this is accomplished by a loop supplying outputs from the second bit position N2 of the suppression register N to an AND gate AG 8 receiving the outputs from the flip-flop B, a loop supplying the outputs from the least significant bit N1 to an AND gate AG 7 receiving the outputs from the flip-flop B, and a loop supplying the output Na to an AND gate AG9. The output from the OR gate 0G 3 closes the AND gate AG 4 and opens the AND gate AG2 upon depression of the numerical key 2. At this time the AND gates AG7, AG8 are opened by the set output from the decision flip-flop B and as a result 1 previously stored in the most significant bit position N16 is taken out as the output Na at the timing T15 and then introduced into the bit positon N16 of the suppression register N via the gates AG 8, 0G5, AGS and 0G 6. In this manner a right shift operation by one bit is completed in the suppression register N. Thereafter, the output 1 from the bit position N1 opens the AND gate AG 7 at the timing T16 to enter into the most signficant bit position N 16 through the gates 06 5, AG 2 and 0G 6.

In the meanwhile, the coded number 2 is repeatedly applied to the AND gate AG 1 and the output from the gate 06 7 detennines the timing of entry thereof into the main register X. Since the gate 0G 7 is controlled by the AND gate AG 9 which in turn is controlled by the gate 1G2, the AND gate AG 1 is opened at the timing T 15 to enter the numerical information 2. Thus, the timing of entry operation in the second key entry mode is under the control of the outputs Na of the register N.

An AND gate AG 10 is provided for constituting a circulation loop in the register X upon key depression. The numeral 1 is entered into the digit position X16 via the gate AG 10 at the timing T 16. The key inputs 1, 2 are continuously entered commencing with the most significant digit position thereby causing the indication tubes DP 16, DP 15 to indicate the key input infonnation l,2,---.

The entry operation of third digit information is carried out in the same manner as the above second entry mode. In this case the outputs of the AND gate AG 9 are provided at the time T 14 and the third digit place information is entered into the digit place X 14 of the main register X. The bit positions N 16, N 15, N 14 of the suppression register N store 1. In other words, the suppression register N is operative to count effective key depression for purpose of avoiding the ineffective indication.

Referring now to FIG. 6, there is illustrated another embodiment wherein numeric l information is consecutively entered into the main register X in the ascending order of significance. Unlike the first embodiment, the timing of entry operation into the main register X is fixed, namely, T

Assume that the first entry is 3 and the second entry 4. When the numerical key 3 is manually depressed, the outputs from the OR gate 063 are applied to inhibition gates 1G 3, 1G 5, and AND gates AG 12, AG 14 to open AND gates AG 12, AG 14. The main register X is ready for entry of key input information. At this time the contents of both the registers N, X are cleared upon closure of the gates 1G 3, 1G 5. The entry control circuit PK produces the entry control signal P to enter the coded numerical information 3 into the register X at the timing T That is, the least significant digit place X1 of the register X stores the numeral 3. Differing from the FIG. 2 embodiment the buffer register XD (one digit capacity) is provided for left shift operation.

In the meanwhile the digit time signal T1 is applied to the suppression register N through the gate AG 12 and thus the least significant bit position N thereof stores 1. The suppresion register N also is provided with a suppression buffer ND for left shift operation. After completion of the first key entry mode the information circulates through a loop N, [C 3 OG 9 -N 16 N,.

Thereafter, upon manual depression of the numeric key 4, the AND gate AG 11 provides its output to the inhibit gates 16 4, 1G 6. Logical conditions for the AND gate AG 14 are met at the timing T allowing the numeral 4 to enter into the register X. At this time the register N stores I with the gate AG 13 opened. The contents 3 of the suppression buffer ND is introduced into the suppression register N through the gate [6 4. The succeeding key entry operations will be carried out in the same manner.

Although the above embodiment shows an example wherein the contents of the register are cleared upon commencement of the first key entry mode, the contents of the register X may be transferred to an additional register.

We claim:

l. A key input information indicating system comprising;

a plurality of keys for entering individual key inputs upon the manual depression thereof in first and second key entry modes;

a series of indicating elements for indicating the entered key input;

a counter responsive to the key inputs for counting the number of the manual depressions of the keys, the outputs of the counter being indicative of the number of key inputs to be actually indicated; and

a connection coupling the counter outputs with the indicating elements thereby inhibiting the indication of insignificant information in the series of the indicating elements;

and detection circuit means connected between said keys and said counter for detecting whether a key depression is concerned with a first key entry mode or a second key entry mode.

2. A key input information indicating system as defined in claim 1 which further comprises a second detection circuit means connected between said keys and said counter for detecting whether a key depression is concerned with the numeral 0, the numerals 1 through 9, or a decimal point 3. A key input information indicating system as defined in claim 1 wherein said indicating element series is of the dynamic drive type and the outputs from said detection circuit means control the avoidance and allowance of the indication in the series of the indicating elements in dynamic fashion.

4. A key input information indicating system as defined in claim 1 which further comprises a register connected to said keys for storing the entered key inputs in a predetermined code notation.

5. A key input information indicating system as defined in claim 4 wherein the outputs from said detection circuit means control the timing of entry operation of the key inputs into said register.

6. A key input information indicating system as defined in claim 2, wherein said indicating element series is of the dynamic drive type and the outputs from the first said detection circuit means control the avoidance and allowance of the indication in the series of the indicating elements in dynamic fashion.

7. A key input information indicating system as defined in claim 2. which further comprises a register connected to said keys for storing the entered key inputs in a predetermined code notation.

8. A key input information indicating system as defined in claim 7, wherein the outputs from the first of said detection circuit means control the timing of entry operation of the key inputs into said register.

9. A key input information entry and indicating system comprising:

a plurality of keys for entering, upon depression of each said key, an input signal associated therewith into said system;

a storage register for storing the key input information entered therein in a predetermined code notation;

a series of indicating elements for indicating the information entered into said system;

counter means responsive to said key input signals for counting the number of depressions of said keys, said counter giving an output indicative of the number of significant key input signals required to be displayed;

a connection coupling said output from said counter means to the indicating elements thereby inhibiting the indication of insignificant information in the series of the indicating elements; and

a first detection circuit connected between said keys and said counter means and said storage register for detecting whether said key depression is in a first key entry mode of operation of said system or a second key entry mode thereof, the entry of a digit being placed into the most or least significant place in the storage register when in the first key entry mode and the entry of succeeding digits being placed into the corresponding places in said storage register other than said most or least significant place thereof when in the second key entry mode.

10. A key input information entry and indicating system as defined in claim 9.

wherein said counter means counts the number of depressions of said keys in the form of binary signals 1 and 0, as said output indicative of the number of significant key input signals required to be displayed; and

said first detection circuit causes the entry of a binary signal 1 into the most or least significant place in said counting means when in said first key entry mode and the entry of succeeding binary signals l into the places in said counter means corresponding to those of said storage register when in said second key entry mode.

11. A key input information entry and indicating system as defined in claim 9 further comprising:

a second detection circuit connected between said keys and said counter means and said storage register for detecting whether the information entered into said system by depression of a given key is associated with a ZERO, a numeral from ONE to NINE or a decimal point.

12. A key input information entry and indicating system as defined in claim 10 further comprising:

a second detection circuit connected between said keys and said counter means and said storage register for detecting whether the information entered into said system by depression of a given key is associated with a ZERO, a numeral from ONE to NINE or a decimal point.

13. A key input information entry and indicating system comprising:

a plurality of keys for entering, upon depression of each said key, an input signal associated therewith into said system;

a storage register for storing the key input information entered therein in a predetermined code notation;

a series of indicating elements for indicating the information entered into said system;

counter means responsive to said key input signals for counting the number of depressions of said keys in the form of binary signals 1 and 0, said counter giving an output indicative of the number of significant key input signals required to be displayed;

a connection coupling said output from said counter means to the indicating elements thereby inhibiting the indication of insignificant information in the series of the indicating elements;

a first detection circuit connected to said keys for detecting whether said key depression is in a first key entry mode of operation of said system or a second key entry mode thereof;

a second detection circuit connected to said keys for detecting whether the information entered into said system by depression of a given key is associated with a ZERO, a numeral from ONE to NINE or a decimal; and

a logical unit connected to said first and said second detection circuits, said storage register and said counter means for clearing away previous contents of said storage register and said counter means and positioning the entry of a digit into the most or least significant place in said storage register and positioning the entry of a binary signal 1 into the most l 0 or least significant place in said counter means, when said system is in the first key entry mode and the information just entered into said system is not associated with a ZERO, and positioning the entry of succeeding digits into the corresponding places in said storage register other than said most or least significant place thereof and positioning the entry of succeeding binary signals 1 into the corresponding places in said counter means other than said most or least significant place thereof, when said system is in said second key entry mode and the information just entered into said system is not associated with a ZERO or the binary signal 1 has been previously entered into said counter means.

i l at 

1. A key input information indicating system comprising; a plurality of keys for entering individual key inputs upon the manual depression thereof in first and second key entry modes; a series of indicating elements for indicating the entered key input; a counter responsive to the key inputs for counting the number of the manual depressions of the keys, the outputs of the counter being indicative of the number of key inputs to be actually indicated; and a connection coupling the counter outputs with the indicating elements thereby inhibiting the indication of insignificant information in the series of the indicating elements; and detection circuit means connected between said keys and said counter for detecting whether a key depression is concerned with a first key entry mode or a second key entry mode.
 2. A key input information indicating system as defined in claim 1 which further comprises a second detection circuit means connected between said keys and said counter for detecting whether a key depression is concerned with the numeral 0, the numerals 1 through 9, or a decimal point ..
 3. A key input information indicaTing system as defined in claim 1 wherein said indicating element series is of the dynamic drive type and the outputs from said detection circuit means control the avoidance and allowance of the indication in the series of the indicating elements in dynamic fashion.
 4. A key input information indicating system as defined in claim 1 which further comprises a register connected to said keys for storing the entered key inputs in a predetermined code notation.
 5. A key input information indicating system as defined in claim 4 wherein the outputs from said detection circuit means control the timing of entry operation of the key inputs into said register.
 6. A key input information indicating system as defined in claim 2, wherein said indicating element series is of the dynamic drive type and the outputs from the first said detection circuit means control the avoidance and allowance of the indication in the series of the indicating elements in dynamic fashion.
 7. A key input information indicating system as defined in claim 2, which further comprises a register connected to said keys for storing the entered key inputs in a predetermined code notation.
 8. A key input information indicating system as defined in claim 7, wherein the outputs from the first of said detection circuit means control the timing of entry operation of the key inputs into said register.
 9. A key input information entry and indicating system comprising: a plurality of keys for entering, upon depression of each said key, an input signal associated therewith into said system; a storage register for storing the key input information entered therein in a predetermined code notation; a series of indicating elements for indicating the information entered into said system; counter means responsive to said key input signals for counting the number of depressions of said keys, said counter giving an output indicative of the number of significant key input signals required to be displayed; a connection coupling said output from said counter means to the indicating elements thereby inhibiting the indication of insignificant information in the series of the indicating elements; and a first detection circuit connected between said keys and said counter means and said storage register for detecting whether said key depression is in a first key entry mode of operation of said system or a second key entry mode thereof, the entry of a digit being placed into the most or least significant place in the storage register when in the first key entry mode and the entry of succeeding digits being placed into the corresponding places in said storage register other than said most or least significant place thereof when in the second key entry mode.
 10. A key input information entry and indicating system as defined in claim
 9. wherein said counter means counts the number of depressions of said keys in the form of binary signals 1 and 0, as said output indicative of the number of significant key input signals required to be displayed; and said first detection circuit causes the entry of a binary signal 1 into the most or least significant place in said counting means when in said first key entry mode and the entry of succeeding binary signals 1 into the places in said counter means corresponding to those of said storage register when in said second key entry mode.
 11. A key input information entry and indicating system as defined in claim 9 further comprising: a second detection circuit connected between said keys and said counter means and said storage register for detecting whether the information entered into said system by depression of a given key is associated with a ZERO, a numeral from ONE to NINE or a decimal point.
 12. A key input information entry and indicating system as defined in claim 10 further comprising: a second detection circuit connected between said keys and said counter means and said storage register for deteCting whether the information entered into said system by depression of a given key is associated with a ZERO, a numeral from ONE to NINE or a decimal point.
 13. A key input information entry and indicating system comprising: a plurality of keys for entering, upon depression of each said key, an input signal associated therewith into said system; a storage register for storing the key input information entered therein in a predetermined code notation; a series of indicating elements for indicating the information entered into said system; counter means responsive to said key input signals for counting the number of depressions of said keys in the form of binary signals 1 and 0, said counter giving an output indicative of the number of significant key input signals required to be displayed; a connection coupling said output from said counter means to the indicating elements thereby inhibiting the indication of insignificant information in the series of the indicating elements; a first detection circuit connected to said keys for detecting whether said key depression is in a first key entry mode of operation of said system or a second key entry mode thereof; a second detection circuit connected to said keys for detecting whether the information entered into said system by depression of a given key is associated with a ZERO, a numeral from ONE to NINE or a decimal; and a logical unit connected to said first and said second detection circuits, said storage register and said counter means for clearing away previous contents of said storage register and said counter means and positioning the entry of a digit into the most or least significant place in said storage register and positioning the entry of a binary signal 1 into the most or least significant place in said counter means, when said system is in the first key entry mode and the information just entered into said system is not associated with a ZERO, and positioning the entry of succeeding digits into the corresponding places in said storage register other than said most or least significant place thereof and positioning the entry of succeeding binary signals 1 into the corresponding places in said counter means other than said most or least significant place thereof, when said system is in said second key entry mode and the information just entered into said system is not associated with a ZERO or the binary signal 1 has been previously entered into said counter means. 